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computer12
- 基于FPGA的八位RISC CPU的设计-FPGA-based RISC CPU design eight ....
dlx
- DLX CPU VHDL CODE UNIVERSITY
risc
- 用Verilog 编写的8位risc cpu，行为级描述，可综合-6 bits risc cpu by Verilog
CONTROL_UNIT
- control unit for multicycle cpu
cpu(FinalWithYS)
- verilog实现的八位CPU，包括乘法、除法以及多种寻址方式。代码中包括测试模块，可以直接在试验箱上运行。-verilog to achieve the eight CPU, including multiplication, division, as well as addressing a variety of ways. Code, including test modules, can be run directly in the chamber.
Simple8bitCPU
- VHDL Source Code for Simple 8-bit CPU
cpu_lynn
- Verilog 实现的 简单 单线程 CPU， 基于计算机组成书目， 思路清晰， 有测试平台。-Verilog realization of a simple single-threaded CPU, the composition of computer-based bibliography, clear lines of thought, a test platform.
cpu16
- Verilog下描述16位CPU，虽然有点简单，但具有一定的可读性，内附夏宇闻老师的8位CPU文档-Verilog descr iption of 16-bit CPU, though a bit simple, but with a certain degree of readability, XIA Yu-Wen teachers containing 8-bit CPU Documentation
DDCA_HDL_Examples
- mpis-CPU的VHDL语言设计，也包含了很多课件和例子。-MPIS-CPU
micro
- 16 cpu design VHDL source code, including alu, clock, memory and other parts of the design
CPU
- Simple 8 bit ALU which subs, adds, ands, ors, nots, ...
cpusimple
- a simple vhdl of cpu
cpu
- nios处理器代码，基于VHDL语言，很难道-nios processor code，vhdl code
cpu25
- 8 bit cpu code using vhdl it performs various operations
8bit_RISC_CPU_RTL_Code
- 8位RISC CPU 内核源码(VERILOG版)-8 bit RSIC CPU RTL code(Verilog)
cpu_16bit
- design cpu 16 bits by verilog HDL.
mipscpu-source
- mips cpu的实现.MIPS是世界上很流行的一种RISC处理器。MIPS公司的R系列就是在此基础上开发的RISC工业产品的微处理器。这些系列产品为很多计算机公司采用构成各种工作站和计算 机系统。 -mips cpu implementation. MIPS is the world' s very popular as a RISC processor. MIPS company' s R series is based on the development of industr
plan
- using the VHDL, 8bit cpu plan